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    Computer Architecture
    COMP3147
    Progress0 / 24 topics
    Topics
    1. Digital Hardware Design: Transistors and Digital logic2. Hardware description languages (Verilog)3. Instruction Set Architecture: Instruction types and mixes4. Addressing modes5. RISC vs. CISC architectures6. Exceptions in instruction sets7. Scalar Pipelines: Data dependencies8. Static scheduling9. Pipeline performance analysis10. VLIW Pipelines: Local scheduling11. Loop unrolling and Software pipelining12. Trace scheduling13. Deferred exceptions and Predicated execution14. IA64 architecture15. Dynamic Pipelines: Dynamical scheduling16. Register renaming17. Speculative execution18. Trace cache19. Thread-Level Parallelism: Cache coherency20. Sequential consistency21. Multithreading22. Symmetric multiprocessing23. Transactional memory24. Data-Level Parallelism: GPU programming
    COMP3147›Trace scheduling
    Computer ArchitectureTopic 12 of 24

    Trace scheduling

    3 minread
    532words
    Beginnerlevel

    ⭐ Trace Scheduling

    1. Definition

    Trace scheduling is a compiler optimization technique used to increase instruction-level parallelism (ILP) across basic blocks by reordering instructions along likely execution paths (traces).

    It is mainly used in VLIW (Very Long Instruction Word) and superscalar architectures to produce statically scheduled code that exploits parallelism beyond a single basic block.


    2. Key Concepts

    1. Trace

      • A trace is a sequence of basic blocks that is likely to execute consecutively during program execution.
      • Usually determined using profiling (branch probabilities).
    2. Goal

      • Schedule instructions along the entire trace to maximize parallel execution and keep functional units busy.
      • Reduces pipeline stalls and idle cycles.
    3. Difference from Local Scheduling

      Feature Local Scheduling Trace Scheduling
      Scope Single basic block Across multiple blocks (trace)
      Parallelism Limited (intra-block) Higher (inter-block)
      Complexity Low High
      Hardware Support Not needed Still static, VLIW-friendly

    3. Steps in Trace Scheduling

    1. Trace Selection

      • Identify the most likely path of execution using branch probabilities.
      • Example: if if branch taken 90% of the time, include it in trace.
    2. Instruction Scheduling Along the Trace

      • Reorder instructions from multiple basic blocks in the trace to exploit parallelism.
      • Use pipeline hazards analysis to prevent RAW/WAR/WAW conflicts.
    3. Compensating Code

      • Instructions moved outside their original blocks may need extra code in other paths to maintain program correctness.
      • Example: If an instruction is scheduled before a branch, add fix-up code in the path not taken.
    4. Register Allocation and Finalization

      • After scheduling, assign registers carefully to avoid conflicts caused by moving instructions across blocks.

    4. Example

    Original code:

    if (x > 0) {
        A = B + C;
    } else {
        D = E + F;
    }
    G = H + I;
    

    Likely trace: if (x > 0) path

    • Trace includes: {A = B + C} → {G = H + I}

    Trace scheduling:

    • Instructions from the else-block {D = E + F} may be moved or compensated in the unlikely path.
    • Instructions are reordered to maximize parallel execution along the likely trace.

    Result:

    • More instructions executed per cycle on a VLIW or superscalar pipeline.
    • Less pipeline idle time.

    5. Advantages

    1. Exploits ILP across basic blocks → higher performance than local scheduling.
    2. Improves VLIW pipeline utilization.
    3. Static scheduling → simpler hardware (no dynamic scheduling needed).

    6. Limitations

    1. Complex compiler algorithm – selecting traces and inserting compensating code is tricky.
    2. Code size increase – compensating code may duplicate instructions in unlikely paths.
    3. Accuracy depends on profiling – mispredicted traces can reduce performance.
    4. Best suited for frequently executed paths.

    7. Comparison: Local Scheduling vs Trace Scheduling vs Software Pipelining

    Feature Local Scheduling Trace Scheduling Software Pipelining
    Scope Single basic block Multiple basic blocks (trace) Single loop, across iterations
    Parallelism Limited High (inter-block) High (loop iterations)
    Complexity Low High Medium to High
    Hardware Requirements None VLIW or statically scheduled None (compiler-based)
    Code Size Overhead Low Medium/High (compensating code) Low to Medium

    8. Exam Summary

    • Trace Scheduling: A compiler technique to maximize ILP across basic blocks by scheduling instructions along likely execution paths (traces).
    • Key idea: Move instructions across blocks, use compensating code for correctness.
    • Used in: VLIW and statically scheduled superscalar architectures.
    • Advantages: High ILP, better pipeline utilization.
    • Limitations: Compiler complexity, code size increase, dependent on profiling accuracy.
    Previous topic 11
    Loop unrolling and Software pipelining
    Next topic 13
    Deferred exceptions and Predicated execution

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