⭐ Scalar Pipelines: Data Dependencies

1. What is a Scalar Pipeline?

Definition

A scalar pipeline is a CPU pipeline that processes one instruction per cycle (ideally) through sequential pipeline stages such as:

1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Execute (EX)
4. Memory Access (MEM)
5. Write Back (WB)

It increases performance by overlapping the execution of multiple instructions.

However, overlapping instructions can cause data dependencies, which lead to pipeline hazards.

---

⭐ 2. What Are Data Dependencies?

Definition

A data dependency (also called data hazard) occurs when one instruction depends on the data or result produced by another instruction.

In pipelines, data dependencies can cause incorrect execution or delays (stalls) because instructions are in different stages of execution simultaneously.

---

⭐ 3. Types of Data Dependencies

There are three types of data dependencies, often asked in exams:

---

1. RAW – Read After Write (True Dependency)

⭐ Most important and most common

Definition

A RAW dependency occurs when an instruction needs to read a value that a previous instruction has not yet written.

Example:

I1: R1 = R2 + R3
I2: R4 = R1 + 5      ; Needs result of I1

Here, I2 depends on I1. If the pipeline executes without care, I2 may read the old value of R1 → incorrect execution.

Impact:

• Causes pipeline stalls
• Solved using forwarding or stalling

---

2. WAR – Write After Read (Anti-Dependency)

Definition

A WAR dependency occurs when a later instruction wants to write to a register before an earlier instruction reads it.

Example:

I1: R5 = R2 + R3    ; Reads R5
I2: R5 = R4 - 1     ; Writes R5 early

If I2 writes R5 before I1 reads it → incorrect.

Impact:

• Occurs in out-of-order pipelines, not in simple scalar pipelines
• Solved using register renaming

---

3. WAW – Write After Write (Output Dependency)

Definition

A WAW dependency occurs when two instructions want to write to the same register.

Example:

I1: R6 = R1 + R2   ; Writes R6
I2: R6 = R3 + R4   ; Also writes R6

If I2 writes before I1, the result of I1 is lost.

Impact:

• Happens only in out-of-order execution or long pipelines
• Solved using register renaming

---

⭐ Summary of Dependency Types

Dependency	Full Name	Meaning	Common?	Solution
RAW	Read After Write	True dependency	Yes	Forwarding, Stalling
WAR	Write After Read	Anti-dependency	Only out-of-order	Register renaming
WAW	Write After Write	Output dependency	Only out-of-order	Register renaming

---

⭐ 4. How Data Dependencies Cause Pipeline Hazards

Data dependencies lead to data hazards, specifically:

1. RAW → Read after Write → Data Hazard

Because data isn't ready in time.

2. WAR and WAW mostly appear in:

• Deep pipelines
• Out-of-order processors
• Superscalar architectures

Scalar pipelines mainly face RAW hazards.

---

⭐ 5. Solutions to Data Dependencies in Scalar Pipelines

1. Pipeline Stalling

Pause pipeline until data is ready.

• Simple but slows the CPU

2. Operand Forwarding (Bypassing)

Send the result directly from one pipeline stage to another before it's written to the register file.

Example:

• Forward from EX of I1 → EX of I2

This is the most important technique in scalar pipelines.

3. Register Renaming

Avoids WAR and WAW hazards using extra registers.

4. Compiler Techniques

• Instruction scheduling
• Loop unrolling

Both reduce pipeline stalls.

---

⭐ 6. Example of RAW Hazard in Pipeline

Consider:

I1: R1 = R2 + R3
I2: R4 = R1 + 1

Pipeline timeline without forwarding:

Cycle	IF	ID	EX	MEM	WB
I1	1	2	3	4	5
I2	2	3	STALL	STALL	6

I2 must wait because R1 is written in cycle 5.

With forwarding → only one stall or zero stalls depending on hardware.

---

⭐ 7. Why Data Dependencies Matter

Data dependencies affect:

• Instruction scheduling
• Compiler optimization
• Pipeline design (forwarding, hazard detection)
• Performance (CPI increases)
• Out-of-order execution complexity

In summary:

Data dependencies are the main challenge for achieving one instruction per cycle in pipelines.

---

⭐ Exam-Friendly Short Notes

• Scalar pipeline: Executes one instruction at a time through pipeline stages.

• Data dependency: When one instruction depends on the result of another.

• Types:

  • RAW: True dependency → major hazard
  • WAR: Anti-dependency → solved by register renaming
  • WAW: Output dependency → also solved by renaming

• Hazards: RAW causes stalls unless forwarding is used.

• Solutions: Forwarding, stalling, register renaming, compiler scheduling.