Hardware Description Languages (HDLs): Verilog

1. What is a Hardware Description Language (HDL)?

Definition

A Hardware Description Language (HDL) is a specialized computer language used to describe, design, model, and simulate digital hardware circuits. HDLs allow engineers to represent hardware at different levels of abstraction—behavioral, structural, and register-transfer level (RTL).

Common HDLs:

• Verilog
• VHDL
• SystemVerilog (extension of Verilog)

---

2. What is Verilog?

Definition

Verilog is a hardware description language used to model digital electronic systems. It enables designers to describe hardware using text-based code and is widely used for RTL design, logic synthesis, and digital simulation.

Verilog is similar in syntax to the C programming language, making it easy to learn.

Key Uses of Verilog

• Designing combinational and sequential logic
• Modeling digital circuits before physical implementation
• Simulating hardware behavior
• Synthesizing RTL into gate-level circuits
• Describing hardware modules for FPGAs and ASICs

---

3. Levels of Abstraction in Verilog

Verilog allows design at multiple levels:

1. Behavioral Level (High-Level)

• Describes what the circuit does, not how it is built
• Uses always blocks, if-else, case statements

Example:

always @(a or b)
    c = a + b;

2. Register Transfer Level (RTL)

• Describes data flow between registers
• Most commonly used level for synthesis

Example:

always @(posedge clk)
    q <= d;

3. Gate Level

• Describes circuits in terms of logic gates
• Used in synthesized netlists

Example:

and(a1, x, y);

4. Switch Level

• Describes MOS transistors (rarely used today)

Example:

nmos(out, in, control);

---

4. Basic Elements of Verilog

1. Module

Definition

A module is the basic building block in Verilog used to represent a hardware component.

Example:

module AND_gate (input a, input b, output y);
    assign y = a & b;
endmodule

2. Ports

These are inputs/outputs of a module:

• input
• output
• inout

3. Data Types

• wire → for combinational connections
• reg → for storage elements (flip-flop behavior)
• integer, real → used in testbenches

4. Operators

Verilog supports:

• Logical operators: &&, ||, !
• Bitwise operators: &, |, ^
• Arithmetic: +, -, *, /
• Relational: ==, !=

---

5. Verilog Constructs

1. assign statement

Used for continuous assignments in combinational logic.

Example:

assign y = a & b;

2. always block

Defines procedures that execute when signals change.

Combinational logic:

always @(*)
    y = a + b;

Sequential logic:

always @(posedge clk)
    q <= d;

3. Initial block

Runs only once during simulation (not synthesizable).

Example:

initial begin
    a = 0;
    b = 1;
end

---

6. Modeling Combinational Logic in Verilog

Example: 2-to-1 Multiplexer

module mux2to1(input a, input b, input sel, output y);
    assign y = sel ? b : a;
endmodule

---

7. Modeling Sequential Logic in Verilog

Flip-Flop Example:

always @(posedge clk)
    q <= d;

Counter Example:

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 0;
    else
        count <= count + 1;
end

---

8. Testbenches in Verilog

Definition

A testbench is a Verilog module written to simulate and verify the functionality of a design. It does not represent real hardware and cannot be synthesized.

Key components:

• initial blocks
• Stimulus generation
• Monitoring outputs ($monitor, $display)

Example:

module testbench();
    reg a, b;
    wire y;

    AND_gate uut(a, b, y);

    initial begin
        a = 0; b = 0;
        #10 a = 1;
        #10 b = 1;
        #10 $finish;
    end
endmodule

---

9. Synthesis vs Simulation

Simulation

• Verifies behavior of the design
• Uses testbenches
• Does not create physical hardware

Synthesis

• Converts Verilog RTL into a gate-level netlist
• Used by FPGA/ASIC tools
• Only synthesizable constructs allowed

---

10. Advantages of Using Verilog

• Allows complex digital designs to be expressed easily
• Supports multiple abstraction levels
• Fast simulation and verification
• Can be synthesized to real hardware
• Industry standard for CPU, FPGA, and ASIC design
• C-like syntax makes it easy to learn

---

11. Applications of Verilog in Computer Architecture

Verilog is used to design:

• ALUs
• Registers and register files
• Control units
• Pipelined datapaths
• Cache controllers
• Memory interfaces
• Entire processors (RISC-V, MIPS, ARM-based designs)

Every modern processor is described and verified using an HDL like Verilog.

---

Summary (Exam-Friendly Notes)

1. HDL is a language used to describe digital hardware.
2. Verilog is a widely used HDL for modeling, simulation, and synthesis.
3. Verilog supports behavioral, RTL, gate-level, and switch-level modeling.
4. Key elements include modules, ports, data types (wire, reg), assign statements, and always blocks.
5. Used for designing combinational and sequential circuits.
6. Testbenches are used for simulation and verification of designs.
7. Verilog is essential in designing CPUs, ALUs, controllers, and digital systems.