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    Current Subject
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    Computer Architecture
    COMP3147
    Progress0 / 24 topics
    Topics
    1. Digital Hardware Design: Transistors and Digital logic2. Hardware description languages (Verilog)3. Instruction Set Architecture: Instruction types and mixes4. Addressing modes5. RISC vs. CISC architectures6. Exceptions in instruction sets7. Scalar Pipelines: Data dependencies8. Static scheduling9. Pipeline performance analysis10. VLIW Pipelines: Local scheduling11. Loop unrolling and Software pipelining12. Trace scheduling13. Deferred exceptions and Predicated execution14. IA64 architecture15. Dynamic Pipelines: Dynamical scheduling16. Register renaming17. Speculative execution18. Trace cache19. Thread-Level Parallelism: Cache coherency20. Sequential consistency21. Multithreading22. Symmetric multiprocessing23. Transactional memory24. Data-Level Parallelism: GPU programming
    COMP3147›Exceptions in instruction sets
    Computer ArchitectureTopic 6 of 24

    Exceptions in instruction sets

    4 minread
    647words
    Beginnerlevel

    ⭐ Exceptions in Instruction Sets

    Definition

    An exception is an unexpected or special event that occurs during the execution of an instruction and requires the CPU to temporarily interrupt normal execution to handle the event.

    Exceptions alter the normal flow of a program due to internal CPU or instruction-related conditions.

    They are handled by special routines called exception handlers or trap handlers.

    Exceptions are part of the ISA (Instruction Set Architecture) because:

    • The ISA defines how exceptions occur,
    • What types exist,
    • How the CPU should respond,
    • Where the handler is located.

    ⭐ Interrupts vs. Exceptions (Quick Difference)

    Feature Interrupt Exception
    Cause External device Internal CPU/instruction error
    Timing After current instruction Usually during the instruction
    Example Keyboard press Divide by zero

    Exceptions are caused inside the CPU. Interrupts come from outside.


    ⭐ Types of Exceptions

    Exceptions can be classified into several categories. These categories commonly appear in exams.


    1. Faults

    Definition

    A fault is an exception that can be repaired, allowing the program to resume execution from the same instruction that caused the exception.

    Examples

    • Page fault (memory page not in RAM)
    • Invalid address
    • Segment fault
    • Missing translation in virtual memory

    Behavior

    • Hardware restarts the faulting instruction after the handler fixes the problem.

    2. Traps

    Definition

    A trap is an exception that occurs intentionally to request a service from the operating system. They represent system calls.

    Examples

    • System call (e.g., Linux syscall)
    • Breakpoint trap (for debugging)
    • Software interrupt

    Behavior

    • Return to the next instruction after the trap.

    3. Aborts

    Definition

    An abort is a severe exception that cannot be corrected; the program cannot resume.

    Examples

    • Hardware failure
    • Corrupted instruction
    • Memory parity error
    • Invalid machine instruction format

    Behavior

    • Program is terminated
    • Often triggers OS-level error message

    4. Asynchronous Exceptions

    Definition

    These occur asynchronously with program execution (rarely considered exceptions, more like interrupts).

    Examples include:

    • Power failure
    • Reset signal

    These are handled similar to interrupts.


    ⭐ Causes of Exceptions in Instruction Sets

    Exceptions can be triggered during instruction execution due to:

    1. Arithmetic Errors

    • Divide by zero
    • Overflow
    • Underflow
    • Invalid floating-point operation

    2. Memory Access Errors

    • Page fault
    • Accessing invalid memory
    • Misaligned memory access

    3. Illegal Instructions

    • Executing undefined opcodes
    • Privileged instruction executed in user-mode

    4. System Calls (Software Requests)

    • Using syscall or trap instructions

    5. Protection Violations

    • Write to read-only memory
    • Accessing kernel memory from user mode

    6. Hardware Failures

    • Parity/ECC errors
    • Cache failure

    ⭐ Exception Mechanism (How CPU Handles Exceptions)

    When an exception occurs:

    Step 1: Save Context

    The CPU saves critical information:

    • Program Counter (PC)
    • Cause of exception
    • Register state

    Step 2: Transfer Control

    The CPU jumps to exception handler located at a specific memory address (defined by the ISA).

    Step 3: Execute Handler

    The OS or hardware:

    • Fixes the error (e.g., loads missing page)
    • Or stops the program if fatal

    Step 4: Resume or Terminate

    • Faults → resume faulty instruction
    • Traps → resume next instruction
    • Aborts → terminate program

    ⭐ Exceptions in RISC Architectures (e.g., MIPS)

    Common exceptions in MIPS:

    • Overflow
    • Address error (misaligned access)
    • Page fault
    • System call (syscall)
    • Breakpoint
    • Reserved instruction

    MIPS uses:

    • Exception Program Counter (EPC) to store the address of the instruction
    • Cause register to store the reason

    ⭐ Exceptions in CISC Architectures (e.g., x86)

    x86 has many exceptions:

    • Divide error
    • Debug trap
    • Breakpoint
    • Overflow trap
    • Invalid opcode
    • Page fault
    • General protection fault
    • Double fault

    It uses the Interrupt Descriptor Table (IDT) to define handlers.


    ⭐ Why Exceptions Are Important in ISA

    1. Support for virtual memory
    2. Protection and security
    3. Error handling
    4. Support for system calls
    5. Smooth interaction between user programs and operating system
    6. Hardware-level fault recovery

    ⭐ Exam-Friendly Summary

    • Exception: An internal, unexpected event during instruction execution.
    • Types: Faults (restart), Traps (next instruction), Aborts (terminate).
    • Causes: Arithmetic errors, illegal opcodes, page faults, system calls.
    • Handling: Save PC, jump to handler, fix or terminate, resume if possible.
    • ISA defines how exceptions are signaled and handled.
    Previous topic 5
    RISC vs. CISC architectures
    Next topic 7
    Scalar Pipelines: Data dependencies

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