⭐ 1. Deferred Exceptions

Definition

A deferred exception (also called precise or delayed exception) is an exception detected during instruction execution but reported later, allowing the processor to maintain precise program state.

The processor continues executing instructions after detecting a potential exception but delays handling it until a safe point where the program state reflects a sequential execution.

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Purpose

• To ensure precise exceptions, meaning:

  1. All instructions before the faulting instruction appear to have executed.
  2. The faulting instruction is the next instruction to execute.
  3. Instructions after the faulting instruction have not executed (from the program’s perspective).

• Important for pipelines and out-of-order execution, where multiple instructions are in flight.

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Example

Consider a pipeline executing instructions:

I1: R1 = A + B
I2: R2 = C / D      <- division by zero occurs
I3: R3 = R1 + R2

• Without deferred exceptions: Exception may occur immediately, leaving I1 complete but I3 partially executed → imprecise state.

• With deferred exceptions:

  • Pipeline allows I3 and other independent instructions to execute.
  • Exception for I2 is reported only when it is safe, ensuring precise state.

Key idea: The program behaves as if instructions executed sequentially, even in a pipelined or out-of-order processor.

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Advantages

1. Maintains precise exceptions in pipelines.
2. Enables out-of-order execution without corrupting program state.
3. Simplifies debugging and OS exception handling.

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Implementation Notes

• Requires hardware support to record instruction addresses and state.
• Exception handling may use a reorder buffer (ROB) in modern CPUs.
• Common in RISC, superscalar, and VLIW architectures.

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⭐ 2. Predicated Execution

Definition

Predicated execution (or conditional execution) is a technique where instructions are executed conditionally based on a Boolean predicate, rather than using explicit branches.

Each instruction has an associated predicate (true/false); the instruction only updates state if the predicate is true.

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Purpose

1. Reduce control hazards in pipelines by minimizing branches.
2. Increase instruction-level parallelism (ILP) in VLIW or superscalar processors.
3. Simplify pipeline scheduling in deeply pipelined architectures.

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Example

Consider a conditional block:

if (x > 0) {
    A = B + C;
} else {
    D = E + F;
}

Without Predication:

• Branch instruction required → pipeline may stall.

With Predication:

• Convert to predicated instructions:

p1 = (x > 0)       ; predicate
A = B + C if p1
D = E + F if !p1

• No branch; all instructions issued in parallel.
• Instructions not meeting the predicate do not update registers/memory.

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Advantages of Predicated Execution

1. Reduces branch misprediction penalties.
2. Enables more instructions to execute in parallel, especially in VLIW.
3. Simplifies loop unrolling and software pipelining.

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Limitations

1. Predicated instructions still occupy pipeline resources, even if predicate is false.
2. Limited predicate registers in hardware.
3. Not suitable for large conditional blocks (code expansion may occur).

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⭐ Comparison

Feature	Deferred Exceptions	Predicated Execution
Purpose	Ensure precise exception reporting	Reduce branches and control hazards
When applied	During exceptions in pipelines	During normal instruction execution
Control flow effect	Postpones exception handling	Conditionally executes instructions
Hardware support	Reorder buffer, pipeline tracking	Predicate registers
Benefit	Maintains sequential program correctness	Increases ILP, reduces stalls

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⭐ Exam Summary

• Deferred Exceptions: Delay exception handling until safe program state is reached; critical for pipelines and out-of-order execution.
• Predicated Execution: Execute instructions conditionally based on a predicate instead of branching; reduces pipeline stalls and control hazards.