ScholarQuill logoScholarQuillUniversity Notes
  • Notes
  • Past Papers
  • Blogs
  • Todo
Login
ScholarQuill logoScholarQuillUniversity Notes
Login
NotesPast PapersBlogsTodo
More
SubjectsDiscussionCGPA CalculatorGPA CalculatorStudent PortalCourse Outline
About
About usPrivacy PolicyReportContact
Notes
Past Papers
Blogs
Todo
Analytics
    Current Subject
    🧩
    Digital Logic Design
    CC-110
    Progress0 / 63 topics
    Topics
    1. Introduction to Digital Systems2. Number Systems3. Introduction to Boolean Algebra4. Basic theorems and properties of Boolean Algebra5. Boolean Functions6. Logic Gates7. NAND and NOR Implementation8. Representation of Function in Sum of Minterms or Product of Maxterms9. Simplification of Boolean function using Karnaugh Map10. Don't care Conditions11. The Tabulation Method12. Introduction to Combinational Logic13. Design of Adders14. Design of Subtractors15. Code Convertors16. Analysis Procedure of Combinational Circuits17. Binary Parallel Adders18. Decimal Adders19. Magnitude Comparator20. Decoders and its applications21. Multiplexers22. Demultiplexers23. Encoders24. ROM25. Programmable Logic Array (PLA)26. Introduction to Sequential Circuits27. Basic Flip Flop28. Clocked RS Flip Flop29. Clocked D Flip Flop30. Clocked JK Flip Flop31. Clocked T Flip Flop32. Analysis of Clocked Sequential Circuits33. State Reduction and Assignment34. Flip Flop Excitation tables35. Design Procedure36. Design of Counters37. Design with State Equations38. Introduction to Registers39. Shift Registers40. Ripple Counters41. Synchronous Counters42. Timing Sequences43. Memory Unit44. Random Access Memory45. Introduction to Programmable Logic Devices (CPLD, FPGA)46. Lab Assignments using tools such as Verilog HDL/VHDL, MultiSim47. Familiarization with Digital Electronic Trainer48. Logic gates operations49. Half Adder Operation50. Full Adder Operation51. Half Subtractor Operation52. Full Subtractor Operation53. 7-Segment Display Operation54. Decoder Operation55. BCD To 7-Segment Display56. Multiplexer Operation57. Using Multiplexer and Demultiplexer/Decoder58. Multiplexing 7-Segment Displays59. Comparator Operations60. D Latch and Flip-Flop Operation61. Latching BCD Data for Displaying On 7-Segment Display62. JK Flip-Flop Operation63. Random Access Memories
    CC-110›Flip Flop Excitation tables
    Digital Logic DesignTopic 34 of 63

    Flip Flop Excitation tables

    4 minread
    615words
    Beginnerlevel

    Flip-flop excitation tables are used to determine the necessary input conditions (or excitation) required to transition a flip-flop from one state to another. A flip-flop is a basic memory element in digital systems, which stores one bit of information. Each flip-flop has a set of inputs, typically called the "inputs" and "clock," and two outputs, usually denoted as Q and Q‾\overline{Q}Q​ (the complement of Q).

    There are different types of flip-flops such as SR (Set-Reset), JK, D, and T flip-flops, and each has its own excitation table that defines how the flip-flop’s inputs (such as S and R for SR, J and K for JK, and so on) must change in order to achieve a desired transition between states.

    Here’s how excitation tables are structured for different types of flip-flops:

    1. SR Flip-Flop

    The SR flip-flop has two inputs: S (Set) and R (Reset). It has two possible outputs: Q and Q‾\overline{Q}Q​.

    Current State (Q) Next State (Qnext) S R
    0 0 0 1
    0 1 1 0
    1 0 0 1
    1 1 1 0
    • Set (S = 1, R = 0): The flip-flop will be set to 1, regardless of the current state.
    • Reset (S = 0, R = 1): The flip-flop will be reset to 0, regardless of the current state.
    • Hold (S = 0, R = 0): The flip-flop holds its current state.
    • Invalid (S = 1, R = 1): This state is not allowed because it leads to an undefined output.

    2. JK Flip-Flop

    The JK flip-flop is a more versatile version of the SR flip-flop, where the inputs are J and K. The table for the JK flip-flop is:

    Current State (Q) Next State (Qnext) J K
    0 0 0 1
    0 1 1 0
    1 0 0 1
    1 1 1 0
    1 Toggle 1 1
    • Set (J = 1, K = 0): The flip-flop will be set to 1.
    • Reset (J = 0, K = 1): The flip-flop will be reset to 0.
    • Hold (J = 0, K = 0): The flip-flop holds its current state.
    • Toggle (J = 1, K = 1): The flip-flop will toggle its state.

    3. D Flip-Flop

    The D flip-flop has a single data input (D) and a clock signal. The D flip-flop stores the value of D at the moment of the clock's rising or falling edge and makes that value available at its output Q.

    Current State (Q) Next State (Qnext) D
    0 0 0
    0 1 1
    1 0 0
    1 1 1
    • The D flip-flop transfers the value of D to Q on the clock's triggering edge (either rising or falling, depending on the specific design).
    • Hold (D = Q): The flip-flop holds its current state.

    4. T Flip-Flop

    The T flip-flop (Toggle flip-flop) has a single input, T. It toggles its state whenever T = 1, and holds its state when T = 0.

    Current State (Q) Next State (Qnext) T
    0 0 0
    0 1 1
    1 0 1
    1 1 0
    • Toggle (T = 1): The flip-flop will toggle its state.
    • Hold (T = 0): The flip-flop holds its current state.

    Purpose of Flip-Flop Excitation Tables

    Excitation tables help designers of digital circuits understand and plan how flip-flops should behave during each clock cycle. By using these tables, the designer can determine which inputs need to be applied to achieve the desired output state transitions. These tables also allow for proper synchronization in sequential circuits, making sure that the flip-flops switch between states at the right time, avoiding errors or undesired behavior in the system.

    Previous topic 33
    State Reduction and Assignment
    Next topic 35
    Design Procedure

    Past Papers

    Open this section to load past papers

    Click on Show Past Papers to see past papers.
    On This Page
      Reading Stats
      Est. reading time4 min
      Word count615
      Code examples0
      DifficultyBeginner