Clocked RS Flip Flop

Clocked RS Flip-Flop

A Clocked RS Flip-Flop is a modified version of the basic SR flip-flop (Set-Reset Flip-Flop) that incorporates a clock input to synchronize the state changes. In a clocked RS flip-flop, the state change occurs only when the clock signal is active. This clocked version prevents unwanted changes in state when the clock signal is not active, allowing for better control and synchronization in sequential circuits.

Basic SR Flip-Flop Recap

The basic SR flip-flop has two inputs:

• Set (S): This input is used to set the output Q to 1.
• Reset (R): This input is used to reset the output Q to 0.
• Q and Q': These are the output and its complement (Q' is the inverse of Q).

The behavior of the basic SR flip-flop is as follows:

• S = 1 and R = 0: Set the output Q to 1.
• S = 0 and R = 1: Reset the output Q to 0.
• S = 0 and R = 0: The flip-flop retains its previous state.
• S = 1 and R = 1: This is an invalid condition for a basic SR flip-flop because both Q and Q' cannot be 1 simultaneously.

Clocked RS Flip-Flop

A Clocked RS flip-flop adds a clock input (C or CLK) to the basic SR flip-flop. The clock signal controls when the state of the flip-flop can change. The flip-flop changes its state only when the clock signal is active, which helps prevent unwanted changes to the state during non-clock periods.

Truth Table for Clocked RS Flip-Flop

The behavior of a clocked RS flip-flop can be summarized in a truth table. Here, the flip-flop only responds to the S and R inputs when the clock (C) is active (usually when the clock signal is high, or the rising edge is triggered).

Clock (C)	S	R	Q (Next State)	Q' (Complement)
0	0	0	No Change	No Change
0	1	0	Q = 1	Q' = 0
0	0	1	Q = 0	Q' = 1
0	1	1	Invalid	Invalid
1	0	0	No Change	No Change
1	1	0	Q = 1	Q' = 0
1	0	1	Q = 0	Q' = 1
1	1	1	Invalid	Invalid

Operation of Clocked RS Flip-Flop

1. Clock Low (C = 0):

   • When the clock is low (inactive), the flip-flop does not change its state, regardless of the S and R inputs. The outputs Q and Q' retain their previous values, essentially ignoring the inputs.
   • This ensures that the state of the flip-flop is only modified during the active clock period, preventing unwanted state changes.

2. Clock High (C = 1):

   • When the clock is high (active), the flip-flop is sensitive to the S and R inputs:
     • S = 1 and R = 0: The output Q is set to 1, and Q' is set to 0.
     • S = 0 and R = 1: The output Q is reset to 0, and Q' is set to 1.
     • S = 0 and R = 0: The flip-flop retains its previous state (no change).
     • S = 1 and R = 1: This is still an invalid condition, just like in the basic SR flip-flop, because both outputs Q and Q' cannot be 1 simultaneously.

Symbol for Clocked RS Flip-Flop

The symbol for the clocked SR flip-flop typically includes:

• Inputs: S (Set), R (Reset), and C (Clock).
• Outputs: Q and Q'.
• The clock input is often shown as a triangle or a "C" next to the flip-flop symbol to indicate that the state change occurs based on the clock signal.

Advantages of Clocked RS Flip-Flop

1. Control Over State Changes:

   • The clocked RS flip-flop ensures that state changes occur only during the active clock period, allowing for better control over the circuit's timing and synchronization. This prevents accidental changes in state when the clock is not active.

2. Simplicity:

   • The clocked SR flip-flop is relatively simple and easy to implement, providing basic memory functionality with a single bit of storage, which is essential for sequential circuits.

3. Prevention of Race Conditions:

   • With the clock input controlling state changes, clocked RS flip-flops help to prevent race conditions and glitches that can occur in purely asynchronous circuits.

Disadvantages of Clocked RS Flip-Flop

1. Invalid State (S = 1 and R = 1):

   • Just like the basic SR flip-flop, the clocked RS flip-flop has an invalid state condition when both S = 1 and R = 1. This creates an undefined output, which limits its use in some applications.

2. Limited Functionality:

   • The clocked SR flip-flop is simple but has limited functionality. In more complex designs, other types of flip-flops like D, JK, or T flip-flops may be needed to handle more complex state transitions.

Applications of Clocked RS Flip-Flop

1. Memory Storage:

   • The clocked RS flip-flop can be used for simple memory storage, storing one bit of information in digital circuits.

2. Control Systems:

   • Clocked RS flip-flops are used in control systems where state transitions need to be synchronized with a clock signal, such as in finite state machines (FSMs).

3. Timers and Counters:

   • It can be used in simple timing circuits or counters, where the state changes need to occur based on a clock pulse.

4. Synchronous Sequential Circuits:

   • The clocked RS flip-flop is an essential building block in synchronous sequential circuits, where state transitions must occur in sync with the clock signal.

Conclusion

A Clocked RS Flip-Flop is an essential element in digital design, providing a controlled, synchronized way to store a single bit of information. By adding a clock input to the basic SR flip-flop, it enables state changes to occur only during specific times, preventing unwanted transitions and ensuring reliable operation in sequential circuits. While it has limitations, such as the invalid state (S = 1 and R = 1), it is still widely used in simple memory storage and control applications.