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    Computer Organization and Assembly Language
    COMP3137
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    Topics
    1. Introduction to Computer Organization2. Assembly Language3. Comparison of Low-Level and High-Level Languages4. Register Types (16-bit): General Purpose and Special Purpose Registers5. Introduction and Usage of RAM6. Processor7. Registers8. System Bus9. Instruction Execution Cycle10. Assembly and Machine Language11. Assembler12. Linker and Link Libraries13. Programmer's View of a Computer System14. RISC and CISC Architecture15. Physical Address Calculation16. Basic Memory Organization17. CPU Organization18. Top Level View of Computer Function and Interconnection19. Assembler Instruction Cycle20. Execute Cycle21. Interrupts22. Interrupt Cycle23. Memory Connection24. Input/Output Connection25. CPU Connection26. MASM27. MIPS28. Defining Data in MASM Assembler29. Elements of Assembly Language30. Integer Constants31. Integer Expressions32. Real Number Constants33. Character Constants34. String Constants35. Reserved Words36. Identifiers37. Directives38. Instructions39. The NOP (No Operation) Instruction40. Adding and Subtracting Integer41. INC and DEC Instructions42. NEG Instruction43. How to Move Integer Number in Register44. Adding and Subtracting Numbers in Registers45. Declaration and Initialization of Variables46. Moving Data from Variable to Register47. Data Definition Statement48. BYTE and SBYTE Data49. WORD and SWORD Data50. Defining DWORD and SDWORD Data51. Knowledge about Different Data Types52. Operations, Array & Loops53. Division and Multiplication in Assembly54. Jumps Based on Specific Flags55. Jumps Based on Equality56. Simple Jump Statements57. Jumps Based on Specific Condition58. Code Examples59. Practice on MASM60. Procedures61. File Operations Procedures62. Labels in Procedures63. Stack64. Runtime Stack65. Conditional Control Flow Directives66. Compound Expressions67. Data Representation & Conversion68. Architecture69. Data Path70. Control Unit71. Critical Path72. General Principles of Pipelining73. Pipelined Y86 Implementations
    COMP3137›Physical Address Calculation
    Computer Organization and Assembly LanguageTopic 15 of 73

    Physical Address Calculation

    7 minread
    1,162words
    Intermediatelevel

    Physical Address Calculation in Computer Systems

    In computer systems, address translation is a process by which the logical address (or virtual address) generated by the CPU is mapped to a physical address in memory. This is a key concept in systems that use virtual memory, as it allows programs to use a larger address space than the physical memory available.

    The physical address refers to the actual location in the main memory (RAM), while the logical address (or virtual address) is the address seen by the program or the CPU. The Memory Management Unit (MMU) is responsible for handling the mapping between logical and physical addresses.

    Let’s break down how physical address calculation works, especially in the context of paging, which is one of the most common memory management techniques.


    Address Translation: Logical Address to Physical Address

    In a system with virtual memory, the logical address generated by the CPU is divided into two parts:

    1. Page number: Determines the page in the virtual address space.
    2. Offset: Specifies the location within the page.

    The physical address is then determined using these components, and this involves looking up a table that stores the mapping between virtual and physical addresses. The translation process can be broken down into several steps:


    Steps in Physical Address Calculation (Paging Example)

    1. Virtual Address Breakdown:

    In a system that uses paging, the virtual address is divided into two parts:

    • Page number (VPN - Virtual Page Number): Identifies which page in the virtual address space the address belongs to.
    • Offset (Page Offset): Identifies the specific byte or word within the page.

    For example:

    • If a virtual address is 32 bits and the system uses pages of 4 KB (4096 bytes), and each address within a page is mapped to a specific byte, the breakdown would look like this:
      • Page size = 4 KB = 2^12 bytes, so the lower 12 bits of the virtual address will represent the offset.
      • The remaining bits will represent the page number.

    2. Translation Lookaside Buffer (TLB) and Page Table Lookup:

    • The TLB is a small, fast cache that stores recent address translations. If the page number is found in the TLB, the physical address can be determined quickly.
    • If the page number is not in the TLB, the system must look up the translation in the page table. The page table is a data structure maintained by the operating system to map virtual page numbers to physical page numbers.

    3. Page Table Entry (PTE):

    Each entry in the page table corresponds to a virtual page and contains the physical page number (PFN - Physical Frame Number) where the data for that virtual page is stored in physical memory. The offset remains the same, since it represents a location within the page.

    4. Physical Address Calculation:

    The physical address is calculated by combining the physical frame number (obtained from the page table) and the offset.

    • Physical Address = (Physical Frame Number) + (Page Offset)

    This means that the physical address is formed by concatenating the physical frame number (from the page table) with the offset within the page.


    Example of Physical Address Calculation

    Let’s consider a system with the following parameters:

    • Virtual address = 32 bits
    • Page size = 4 KB (4096 bytes)
    • Physical memory = 64 MB (2^26 bytes)
    • Number of pages = 2^20 (since 4 KB pages are used)

    Now, let's say we have a virtual address: 0x00401A7F.

    1. Break the Virtual Address into Components:

      • Page size = 4 KB = 2^12 bytes.
      • Therefore, the offset is 12 bits (since 2^12 = 4096 bytes).
      • The remaining 20 bits represent the virtual page number (VPN).

      So, the virtual address 0x00401A7F can be broken down as:

      • VPN (Virtual Page Number) = 0x00401 (upper 20 bits)
      • Offset = 0xA7F (lower 12 bits)
    2. Translate the VPN to a Physical Frame Number (PFN):

      • The MMU will use the page table to translate the VPN into a physical frame number (PFN).
      • Suppose, in this case, the page table maps VPN 0x00401 to PFN 0x000F (This is an example of a page table lookup).
    3. Combine the PFN with the Offset:

      • The offset remains unchanged because it is the position within the page.

      • Therefore, the physical address is formed by combining the PFN (0x000F) with the offset (0xA7F):

        Physical Address = (PFN << 12) + Offset

        • PFN = 0x000F (physical page frame number)
        • Offset = 0xA7F (page offset)

        So, the physical address calculation would be:

        Physical Address = (0x000F << 12) + 0xA7F = 0x000F000 + 0xA7F = 0x000F07F

    4. Final Physical Address:

      • The physical address corresponding to the virtual address 0x00401A7F would be 0x000F07F in physical memory.

    General Formula for Physical Address Calculation

    Given:

    • Virtual Address = [VPN (Virtual Page Number) | Offset]
    • Page size = 2n2^n2n bytes, where nnn is the number of bits for the offset.
    • The page table maps each VPN to a physical frame number (PFN).

    The physical address is calculated as:

    Physical Address=(PFN)×2n+Offset\text{Physical Address} = \left( \text{PFN} \right) \times 2^n + \text{Offset}Physical Address=(PFN)×2n+Offset

    Where:

    • PFN is the physical frame number obtained from the page table.
    • Offset is the lower part of the virtual address (representing the location within the page).
    • 2n2^n2n represents the number of bytes in a page (for a 4 KB page, n = 12).

    Example with Multiple Levels of Paging (Multilevel Page Tables)

    In more advanced systems, multilevel page tables are used to manage larger address spaces. Instead of having a single page table that maps virtual pages directly to physical frames, the virtual address is divided into multiple levels:

    1. Level 1: First-level page table (maps large blocks of virtual memory to second-level page tables).
    2. Level 2: Second-level page table (maps smaller blocks of virtual memory to actual physical frames).

    In this case, the calculation would involve looking up multiple page tables (each corresponding to different parts of the virtual address) before combining the results to generate the physical address.

    For example, in a system with 32-bit virtual addresses and a 2-level page table:

    • The first-level page table would be used to map the upper portion of the virtual address (the higher-order bits).
    • The second-level page table would map the remaining bits to a physical frame.

    Summary

    The calculation of a physical address involves:

    1. Breaking the virtual address into a virtual page number (VPN) and an offset.
    2. Using the page table to map the VPN to a physical frame number (PFN).
    3. Combining the PFN and offset to form the final physical address.

    In systems that use paging, this mapping allows the operating system to manage memory efficiently, enabling processes to have their own address spaces and supporting virtual memory, even when the system has limited physical memory.

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    Basic Memory Organization

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      Est. reading time7 min
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      DifficultyIntermediate