MIPS

MIPS (Microprocessor without Interlocked Pipeline Stages)

MIPS is a family of RISC (Reduced Instruction Set Computing) microprocessor architectures developed by MIPS Computer Systems. MIPS processors are widely used in embedded systems, networking equipment, game consoles, and academic settings due to their simplicity, efficiency, and clean architecture.

Key Features of MIPS Architecture

1. RISC Architecture: MIPS follows the RISC (Reduced Instruction Set Computing) design philosophy, which means that it uses a small, simple set of instructions that can execute very quickly, typically in one clock cycle. The goal of RISC is to simplify the design of processors and improve performance by optimizing common tasks.

2. Fixed-Length Instructions: MIPS instructions are fixed-length (usually 32 bits), meaning every instruction is the same size, which simplifies instruction decoding and pipeline design.

3. Three Types of Instructions: MIPS instructions are divided into three main formats:

   • R-type (Register): These instructions perform operations between registers. They typically do not involve memory addresses.
   • I-type (Immediate): These instructions involve an immediate value (a constant value) and a register.
   • J-type (Jump): These instructions are used for jumps (branching) in the code, such as jumping to a different part of the program.

4. Load/Store Architecture: MIPS is a load/store architecture, meaning that all operations (like addition or subtraction) happen between registers, and memory can only be accessed using special load and store instructions (e.g., LW for loading a word, SW for storing a word). This reduces complexity and optimizes performance.

5. Pipelining: MIPS processors are designed to support pipelining, a technique that allows multiple instruction stages (fetch, decode, execute, memory access, and write-back) to be overlapped. This increases instruction throughput and helps achieve high performance.

6. Register-Based Operations: MIPS uses a large set of registers. Typically, MIPS architecture has 32 general-purpose registers, numbered $0 to $31. These registers are used to store values temporarily during the execution of instructions.

   • $0 is a constant register that always contains the value 0.
   • $31 is often used as the return address for function calls.
   • Other registers are used for general-purpose storage, function arguments, return values, etc.

7. Simple and Clean Design: MIPS processors are known for their simplicity in design, which makes them easy to implement and understand. The clean design also facilitates optimizations like branch prediction, out-of-order execution, and superscalar execution (where multiple instructions are processed per cycle).

MIPS Instruction Formats

MIPS instructions come in three primary formats: R-type, I-type, and J-type. Each type of instruction has a specific format that dictates how the instruction is structured and what operations it can perform.

1. R-type (Register) Instruction Format

R-type instructions perform operations between two registers and store the result in a third register. They are used for operations like arithmetic, logic, and shifts.

Format:

opcode (6 bits) | rs (5 bits) | rt (5 bits) | rd (5 bits) | shamt (5 bits) | funct (6 bits)

• opcode: 6 bits that specify the operation.
• rs: 5 bits that specify the first register (source register).
• rt: 5 bits that specify the second register (source register).
• rd: 5 bits that specify the destination register (where the result is stored).
• shamt: 5 bits for shift amount (used in shift operations).
• funct: 6 bits that specify the exact operation (e.g., add, subtract, shift, etc.).

Example: add $t0, $t1, $t2

• This adds the contents of registers $t1 and $t2 and stores the result in $t0.
• This instruction is represented in the R-type format.

2. I-type (Immediate) Instruction Format

I-type instructions are used for operations that involve an immediate value (a constant) and a register. They are typically used for arithmetic with immediate values, load/store operations, and branches.

Format:

opcode (6 bits) | rs (5 bits) | rt (5 bits) | immediate (16 bits)

• opcode: 6 bits that specify the operation.
• rs: 5 bits for the source register.
• rt: 5 bits for the destination register (where the result is stored).
• immediate: 16-bit constant value used in the operation.

Example: addi $t0, $t1, 5

• This adds the immediate value 5 to the contents of register $t1 and stores the result in $t0.

Example: lw $t0, 4($t1)

• This loads a word from memory, using the address 4 + $t1, into register $t0.

3. J-type (Jump) Instruction Format

J-type instructions are used for jump operations, which modify the flow of execution. They specify a target address for jumps or branches.

Format:

opcode (6 bits) | address (26 bits)

• opcode: 6 bits that specify the jump operation (such as j for jump).
• address: 26 bits that specify the target address of the jump.

Example: j target

• This jumps to the specified target address in the program.

Common MIPS Instructions

Here are some examples of commonly used MIPS instructions:

1. Arithmetic Instructions:

   • add $t0, $t1, $t2: Adds the values in registers $t1 and $t2, stores the result in $t0.
   • sub $t0, $t1, $t2: Subtracts the value in $t2 from $t1, stores the result in $t0.

2. Load/Store Instructions:

   • lw $t0, 0($t1): Loads a word from memory at the address 0 + $t1 into register $t0.
   • sw $t0, 0($t1): Stores the value in register $t0 into memory at the address 0 + $t1.

3. Branch Instructions:

   • beq $t0, $t1, label: Branches to label if the contents of registers $t0 and $t1 are equal.
   • bne $t0, $t1, label: Branches to label if the contents of registers $t0 and $t1 are not equal.

4. Jump Instructions:

   • j target: Jumps to the target address specified by the instruction.

5. Shift Instructions:

   • sll $t0, $t1, 2: Shifts the value in $t1 left by 2 bits and stores the result in $t0.
   • srl $t0, $t1, 2: Shifts the value in $t1 right by 2 bits and stores the result in $t0.

MIPS Register Usage

MIPS processors have 32 general-purpose registers ($0 to $31). The registers are used for different purposes, and some are reserved for specific roles in the architecture.

• $0: Always contains 0.
• $1** to **$3: Return values for function calls (used in calling conventions).
• $4** to **$7: Arguments for function calls (also used in calling conventions).
• $8** to **$15: Temporary registers ($t0 to $t7).
• $16** to **$23: More temporary registers ($s0 to $s7).
• $24** to **$25: More temporary registers ($t8 and $t9).
• **$29**: Stack pointer (`$sp`).
• **$30**: Link register (`$ra`), stores the return address for function calls.
• $31: Used for function returns and is often involved in storing return addresses.

Advantages of MIPS

1. Simplicity: The MIPS architecture is relatively simple, which makes it easy to understand and implement. This simplicity also makes it easier to optimize the processor for high performance.
2. Speed: Because MIPS uses a RISC design, it executes instructions in a pipeline with minimal stages, typically one per instruction. This leads to faster execution and more efficient use of clock cycles.
3. Scalability: MIPS processors are highly scalable. The architecture has been used in everything from simple embedded systems to high-performance servers.
4. Academic Use: MIPS is often used in educational settings to teach students about computer architecture and assembly language because of its clean and simple design.

MIPS in Practice

MIPS architecture